AI accelerator cards and high-performance computing have pushed 2.5D/3D packaging to full utilisation, tightening ABF substrates, CoWoS-class processes and high-end test slots at the same time. Many projects slip not because the die is missing but because assembly and test cannot be scheduled.
The practical effect is that long lead time has moved from “the chip” to “the package”. The same die in FCBGA may run 30 weeks; in another package, 16 weeks — with thermal and performance re-evaluation required.
Include package and substrate availability in device selection, and reserve capacity rather than only quantity for critical parts. Annotate package type and an alternate package in the BOM, so a shortage decision becomes “change the part” or “change the package” instead of a scramble.